1. Field of the Invention
The present invention relates to a multiplier circuit and a division circuit, and more particularly, to those equipped with a round-off function.
2. Description of the Prior Art
FIGS. 21 and 22 are circuitry diagrams each showing a partial structure of a conventional multiplier circuit 100. In combination, FIGS. 21 and 22 show the entire structure of the multiplier circuit 100.
A multiplicand 1a (=A.sub.3 A.sub.2 A.sub.1 A.sub.0) and a multiplier 1b (=B.sub.3 B.sub.2 B.sub.1 B.sub.0) which are to be given to the multiplier circuit 100 are each expressed in binary 4 bits. The multiplicand 1a and the multiplier 1b are multiplied at a carry-save multiplier part 30 to yield a first multiplication result 4 (=P'.sub.7 P'.sub.6 P'.sub.5 P'.sub.4 P'.sub.3 P'.sub.2 P'.sub.1 P'.sub.0). The sixth most significant bit of the multiplication result 4 is rounded off at a fraction rounding-off circuit 5, whereby a binary 5-bit second multiplication result 2 (=P.sub.7 P.sub.6 P.sub.5 P.sub.4 P.sub.3) is obtained. As herein used, a subscription i of data (=0, 1, 2, 3) represents the digit of 2.sup.i. "To round off" means to calculate a round number, and corresponds to rounding off of the fractions in the decimal system.
The multiplier part 30 is formed by a partial product generating part 30a and an addition processing part 30b. The partial product generating part 30a generates a partial product group 6 from the multiplicand 1a and the multiplier 1b. The addition processing part 30b performs a carry-save addition using half adders 7a to 7c, full adders 8a to 8f and a carry look ahead high-speed adder 9 while aligning the digits of the partial product group 6. The dotted grids in the addition processing part 30b represent how the digits are aligned and stages at which an addition is performed.
FIG. 23 is a circuitry diagram showing a structure of a conventional division circuit 200. A dividend A and a divisor B which are to be given to the division circuit 200 are each expressed in binary 8 bits and satisfy a relation A&lt;B. The dividend A and the divisor B are supplied to a 9-bit division circuit 10 which calculates a quotient Q' which includes decimal 9 bits. The quotient Q' is given to the rounding circuit 5 which rounds off the decimal ninth bit of the quotient Q' and outputs an 8-bit quotient Q.
FIG. 24 is a circuitry diagram showing the details of the 9-bit division circuit 10. The 9-bit division circuit 10 comprises 1-bit quotient determining circuits 12a, 12b, . . . 12i. First, 9-bit data which is obtained by adding 0 to the lower bit side of the dividend A is divided by the divisor B at the 1-bit quotient determining circuit 12a, and the resulting most significant bit is determined as a 1-bit quotient q'.sub.8. At the same time, an 8-bit remainder R.sub.8 is calculated.
Next, 9-bit data which is obtained by adding 0 to the lower bit side of the 8-bit remainder R.sub.8 is divided by the divisor B at the 1-bit quotient determining circuit 12b, and the resulting most significant bit is determined as a 1-bit quotient q'.sub.7 and a remainder R.sub.7 is calculated. In this manner, 1-bit quotients are serially calculated until a 1-bit quotient q'.sub.0 is finally calculated. Thus, the 9-bit quotient Q' (=q'.sub.8 q'.sub.7 q'.sub.6 q'.sub.5 q'.sub.4 q'.sub.3 q'.sub.2 q'.sub.1 q'.sub.0) is found.
Having such structures as above, the conventional multiplier circuit and the conventional division circuit need a rounding circuit, which results in an increase in the number of process stages, a larger circuit size and a delayed operation speed.